module axi_master #(
    parameter DATA_WIDTH = 128,  // 改为128位
    parameter ADDR_WIDTH = 32,
    parameter BURST_LEN_WIDTH = 8  // 保持8位以支持最多256次突发
)(
    // Clock and reset
    input wire clk,
    input wire reset_n,
    
    // AXI Write Address Channel
    output reg [ADDR_WIDTH-1:0] awaddr,
    output reg [7:0] awlen,        
    output reg [2:0] awsize,       
    output reg [1:0] awburst,      
    output reg awvalid,
    input wire awready,
    
    // AXI Write Data Channel
    output reg [DATA_WIDTH-1:0] wdata,
    output reg [DATA_WIDTH/8-1:0] wstrb,  // 自动调整为16位 (128/8)
    output reg wlast,
    output reg wvalid,
    input wire wready,
    
    // AXI Write Response Channel
    input wire [1:0] bresp,
    input wire bvalid,
    output reg bready,
    
    // AXI Read Address Channel
    output reg [ADDR_WIDTH-1:0] araddr,
    output reg [7:0] arlen,        
    output reg [2:0] arsize,       
    output reg [1:0] arburst,      
    output reg arvalid,
    input wire arready,
    
    // AXI Read Data Channel
    input wire [DATA_WIDTH-1:0] rdata,
    input wire [1:0] rresp,
    input wire rlast,
    input wire rvalid,
    output reg rready,
    
    // User interface
    input wire start,
    input wire read_write,          
    input wire [ADDR_WIDTH-1:0] addr,
    input wire [BURST_LEN_WIDTH-1:0] burst_len,
    input wire [2:0] burst_size,   
    input wire [1:0] burst_type,   
    input wire [DATA_WIDTH-1:0] write_data,
    input wire write_data_valid,  // 写数据有效信号
    output reg write_data_ready,  // 写数据就绪信号
    output reg [DATA_WIDTH-1:0] read_data,
    output reg done,
    output reg error
);

// FSM states
localparam [2:0] IDLE       = 3'b000;
localparam [2:0] WRITE_ADDR = 3'b001;
localparam [2:0] WRITE_DATA = 3'b010;
localparam [2:0] WRITE_RESP = 3'b011;
localparam [2:0] READ_ADDR  = 3'b100;
localparam [2:0] READ_DATA  = 3'b101;

reg [2:0] state;
reg [2:0] next_state;
reg [BURST_LEN_WIDTH-1:0] burst_counter;
reg [DATA_WIDTH-1:0] data_buffer [0:255];  // 支持最多256个128位数据
reg [BURST_LEN_WIDTH-1:0] data_count;     // 已接收的数据计数

// 状态机
always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        state <= IDLE;
        awvalid <= 1'b0;
        wvalid <= 1'b0;
        bready <= 1'b0;
        arvalid <= 1'b0;
        rready <= 1'b0;
        done <= 1'b0;
        error <= 1'b0;
        burst_counter <= 0;
        data_count <= 0;
        write_data_ready <= 1'b0;
    end else begin
        state <= next_state;
        
        // Default values
        done <= 1'b0;
        
        case (state)
            IDLE: begin
                if (start) begin
                    if (read_write) begin
                        // Read operation
                        next_state <= READ_ADDR;
                        arvalid <= 1'b1;
                        araddr <= addr;
                        arlen <= burst_len - 1;
                        arsize <= burst_size;
                        arburst <= burst_type;
                    end else begin
                        // Write operation - 先接收数据到缓冲区
                        write_data_ready <= 1'b1;
                        data_count <= 0;
                        next_state <= WRITE_ADDR;
                    end
                end
            end
            
            WRITE_ADDR: begin
                // 等待所有数据接收完成
                if (data_count >= burst_len) begin
                    awvalid <= 1'b1;
                    awaddr <= addr;
                    awlen <= burst_len - 1;
                    awsize <= burst_size;
                    awburst <= burst_type;
                    write_data_ready <= 1'b0;
                    
                    // 准备第一个写数据
                    wvalid <= 1'b1;
                    wdata <= data_buffer[0];
                    wstrb <= 16'b1111111111111111;  // 128位数据需要16个字节使能
                    burst_counter <= 1;
                    if (burst_len == 1)
                        wlast <= 1'b1;
                    else
                        wlast <= 1'b0;
                        
                    next_state <= WRITE_DATA;
                end else if (write_data_valid && write_data_ready) begin
                    // 接收数据到缓冲区
                    data_buffer[data_count] <= write_data;
                    data_count <= data_count + 1;
                end
            end
            
            WRITE_DATA: begin
                if (wvalid && wready) begin
                    if (burst_counter < burst_len) begin
                        // 准备下一个写数据
                        burst_counter <= burst_counter + 1;
                        wdata <= data_buffer[burst_counter];
                        if (burst_counter == burst_len - 1)
                            wlast <= 1'b1;
                    end else begin
                        wvalid <= 1'b0;
                        wlast <= 1'b0;
                        next_state <= WRITE_RESP;
                        bready <= 1'b1;
                    end
                end
            end
            
            WRITE_RESP: begin
                if (bvalid && bready) begin
                    bready <= 1'b0;
                    done <= 1'b1;
                    error <= (bresp != 2'b00);
                    next_state <= IDLE;
                end
            end
            
            READ_ADDR: begin
                if (arvalid && arready) begin
                    arvalid <= 1'b0;
                    next_state <= READ_DATA;
                    rready <= 1'b1;
                    burst_counter <= 0;
                end
            end
            
            READ_DATA: begin
                if (rvalid && rready) begin
                    // Store read data
                    data_buffer[burst_counter] <= rdata;
                    burst_counter <= burst_counter + 1;
                    
                    if (rlast) begin
                        rready <= 1'b0;
                        done <= 1'b1;
                        error <= (rresp != 2'b00);
                        read_data <= rdata;
                        next_state <= IDLE;
                    end
                end
            end
            
            default: begin
                next_state <= IDLE;
            end
        endcase
    end
end

endmodule